Verilog
SystemVerilog
OOP
1 2 |
面向对象的基本概念:类,对象,句柄,类成员,类方法; 类的三大属性:封装,继承,多态。 |
Verification
UVM
技能树
数字IC所需掌握的几项技能:
1.前端
2.后端
3.DFT
4.低功耗设计
5.数字验证方法学
所需掌握的语言、命令:
1、gvim
2、Tcl
3、Makefile
4、Linux
5、Verilog
6、Perl
7、Python
所需掌握的EDA工具:
(EDA工具的教程可以在公众号菜单中找到哟)
1.rtl检查:nLint、LEDA、SpyGlass
2.动态仿真:Modelsim、VCS
3.Debug工具:Verdi
4.逻辑综合:Design Compiler
5.形式验证:Formality
6.布局布线:Synopsys公司的ICC、Astro,Cadence公司的Encounter、Innovus,Mentor公司的Olympus等
7.静态时序分析:PT
8.功耗分析:PTPX
9.DRC LVS:Calibre
10.Memory Compiler:Verisilicon公司的MC、Synopsys公司的Embedit Integrator、ARM公司的Artisan
语言类
Verilog-2001 / VHDL
SystemVerilog / UVM / SystemC
Makefile / Perl / Python / Shell
Tcl
工具类
NCVerilog / VCS / ModelSim
SimVision / DVE / Verdi
Vim / Emacs
SVN / CVS / Git
Microsoft Office
平台类
Windows
Linux
文件和目录操作
- cd
- ls
- find
- pwd
- grep
- mkdir
- touch
- cp
- rm
- mv
- ln
- cat
- more
- head
- less
- tail
- tree
- echo
- which
压缩和解压
- tar
系统相关
- top
- kill
- df
- du
- chmod
其他加分项目
MATLAB
ISE / Synplify / Vivado / Quartus
LEC / Formality
ESL
ZeBu Server
JIRA/ Confluence
C/ Assembly Language
Computer Architecture/ ARM Architecture/ MIPS Architecture
开源项目
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riscv-formal is a framework for formal verification of RISC-V processors.
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Collection of Ethernet-related components for both gigabit and 10G packet processing
Analog Devices Inc. HDL Analog Devices Inc. HDL libraries and projects.
OH Open Hardware for Chip Designers
Hummingbird E200 Opensource Processor Core The Hummingbird E200 core is a two-stages pipeline based ultra-low power/area implementation, which has both performance and areas benchmark better than ARM Cortex-M0+ core, makes the Hummingbird E200 as a perfect replacement for legacy 8051 core or ARM Cortex-M cores in the IoT or other ultra-low power applications.
DarkRISCV opensouce RISC-V implemented from scratch in one night!
wbuart32 Another Wishbone Controlled UART
NVDLA Open Source Hardware The NVIDIA Deep Learning Accelerator (NVDLA) is a free and open architecture that promotes a standard way to design deep learning inference accelerators.